1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to packaged semiconductor memory placed in slots that mirror each other on opposing sides of a four layer printed circuit board to optimize the inter-memory and controller-to-memory routing lengths.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
There are numerous types of memories available in the marketplace. For example, large volumes of data can be stored in magnetic memory, such as a hard disk drive. Lesser quantities of data can be stored in memory arranged upon an integrated circuit, oftentimes referred to as “semiconductor memory.” Semiconductor memory is typically arranged closer to the core logic unit or execution unit than the hard disk drive and can be accessed much faster than the disk drive.
Common to semiconductor memory is an array of storage cells. Depending on the function of the semiconductor memory, each storage cell can have a significantly different architecture and function. For example, semiconductor memory can be volatile or non-volatile. Types of volatile memory include memory which must be periodically refreshed (DRAMs) or memory which will lose its programmed state if power is removed (SRAMs).
The differences between SRAMs and DRAMs are fairly significant. For example, each cell of SRAM includes a latch and pass transistors. Conversely, each cell of DRAM involves simply one transistor. While DRAMs are significantly denser than SRAMs, DRAMs require additional support circuitry to coordinate the access of each cell, along with the need to periodically refresh that cell. Since SRAMs typically have faster access times than DRAMs, SRAMs are oftentimes used as the primary cache of the microprocessor or execution unit. DRAMs, on the other hand, are generally used as the main semiconductor memory and are controlled by a memory controller linked to the execution unit typically by a memory bus or system bus. Each transaction between the execution unit and the memory involves a particular bus cycle. Transfers to and from memory are, therefore, synchronized to the clock cycle of the system clock.
There are numerous types of DRAMs, some of which are: fast page mode DRAMs, extended data out DRAMs, burst extended data out DRAMs, and the more recent synchronous DRAMs (SDRAMs). Unlike DRAMs, SDRAMs take advantage of the fact that memory accesses by the execution unit are typically sequential. SDRAMs are designed to fetch all bits within a particular burst in sequential fashion by allowing the column address to be incremented sequentially and in sync with the system clock of the execution unit or processor. This allows an SDRAM one important advantage over other forms of asynchronous DRAMs—data transfer delivery from the SDRAM at burst rates exceeding, for example, 100 MHz.
With the increased access time speed of the SDRAM came yet another enhancement. Instead of providing source-synchronous data capture at the clock frequency, double data rate (DDR) SDRAM allows data to be captured at a rate of twice the system clock frequency. This is accomplished by utilizing a 2n-prefetch architecture, where the internal data bus of the DDR SDRAM is twice the width of the external data bus to allow data capture of twice per system clock cycle. Details of the difference between a single data rate (SDR) SDRAM and DDR SDRAM are set forth in “General DDR SDRAM Functionality,” Micron Technology 2001 (herein incorporated by reference).
While both SDR and DDR SDRAM include the same core memory array of cells, the input/output (I/O) interface is considerably different. For example, DDR SDRAM utilizes a differential pair of system clock signals to formulate the triggering rising and falling clock edges, and data strobe signals are needed to drive the data signal to and from the SDRAM memory banks. In addition to its double data rate synchronous operation, SDRAMs can employ memory banks, similar to virtual channels used in DRAM technology. The size of the memory bank can vary and, depending on the overall capacity of the memory module, a memory bank can possibly include an entire semiconductor memory device.
Most modern semiconductor memory units are configured as a memory module, where multiple memory integrated circuits are placed upon a printed circuit board (PCB). An example of a PCB having multiple DRAM or SDRAM semiconductor memory devices is generally known as a single in-line memory module (SIMM) or dual in-line memory module (DIMM). A significantly fast memory module thereby includes multiple SDRAM semiconductor devices (or integrated circuit chips) placed on a PCB or DIMM, with edge connectors that slide into a bus receptacle. Each SDRAM can be operated as a DDR SDRAM and can utilize two or more banks of memory arrays which permit interleaving data between the banks to further reduce access times.
Conventional SIMMs or DIMMs that utilize DDR SDRAMs typically involve placing the SDRAMs semiconductor memory devices on only one surface. At the relatively high speeds at which data is sent to and from each memory device, any mismatch in trace length between, for example, a controller and the memory devices, will deleteriously affect performance of the memory module. Thus, lengthy trace conductors associated with some memory devices and relatively short trace conductors associated with others will degrade the overall performance and access times of the SDRAM—an unfortunate event considering the goal of DDR SDRAM with multiple banks is to increase the access times.